An electrical evaluation method for the silicidation of silicon nanowires

X. Tang, N. Reckinger, V. Bayot, D. Flandre, E. Dubois, D.A. Yarekha, G. Larrieu, A. Lecestre, J. Ratajczak, N. Breil, V. Passi, J.-P. Raskin

    Research output: Contribution to journalArticlepeer-review

    Abstract

    Physical and electrical properties of PtSi nanowires (NWs) fabricated on a silicon-on-insulator wafer are investigated. The Si consumption rule in NW silicidation is consistent with that of planar process. The cross-sectional area ratio between PtSi NW and Si NW is about 1.5:1. An electrical method is used to evaluate the silicidation degree of NWs. According to the dependence of the current passing through the NW on the backside substrate voltage, we can determine whether the Si NW is fully or partially silicided. The electrical evaluation results are in agreement with transmission electron microscopy inspections.
    Original languageEnglish
    JournalApplied Physics Letters
    Volume95
    Issue number2
    DOIs
    Publication statusPublished - 1 Jan 2009

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