Very low Schottky barrier to n-type silicon with PtEr-stack silicide

X. Tang; J. Katcki; Emmanuel Dubois; N. Reckinger; J. Ratajczak; G. Larrieu; P. Loumaye; O. Nisole; V. Bayot

doi:10.1016/S0038-1101(03)00256-9

Very low Schottky barrier to n-type silicon with PtEr-stack silicide

X. Tang, J. Katcki, Emmanuel Dubois, N. Reckinger, J. Ratajczak, G. Larrieu, P. Loumaye, O. Nisole, V. Bayot

Research output: Contribution to journal › Article › peer-review

Abstract

We investigate Er silicide formed on n-type silicon. In order to protect the Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at temperatures lower than 700 °C. We find that silicidation process is fully completed by rapid thermal annealing at 500 °C. A simplified method of analysis considering the final Schottky barrier MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low apparent Schottky barrier (smaller than 0.1 eV) on a n-type silicon substrate with a concentration of 1.4×10 cm in the active region has been obtained.

Original language	English
Pages (from-to)	2105-2111
Number of pages	7
Journal	Solid-State Electronics
Volume	47
Issue number	11
DOIs	https://doi.org/10.1016/S0038-1101(03)00256-9
Publication status	Published - 1 Nov 2003

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@article{f81dd5ad04f644c1a51efd8a5353200a,

title = "Very low Schottky barrier to n-type silicon with PtEr-stack silicide",

abstract = "We investigate Er silicide formed on n-type silicon. In order to protect the Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at temperatures lower than 700 °C. We find that silicidation process is fully completed by rapid thermal annealing at 500 °C. A simplified method of analysis considering the final Schottky barrier MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low apparent Schottky barrier (smaller than 0.1 eV) on a n-type silicon substrate with a concentration of 1.4×10 cm in the active region has been obtained.",

author = "X. Tang and J. Katcki and Emmanuel Dubois and N. Reckinger and J. Ratajczak and G. Larrieu and P. Loumaye and O. Nisole and V. Bayot",

year = "2003",

month = nov,

day = "1",

doi = "10.1016/S0038-1101(03)00256-9",

language = "English",

volume = "47",

pages = "2105--2111",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Limited",

number = "11",

}

TY - JOUR

T1 - Very low Schottky barrier to n-type silicon with PtEr-stack silicide

AU - Tang, X.

AU - Katcki, J.

AU - Dubois, Emmanuel

AU - Reckinger, N.

AU - Ratajczak, J.

AU - Larrieu, G.

AU - Loumaye, P.

AU - Nisole, O.

AU - Bayot, V.

PY - 2003/11/1

Y1 - 2003/11/1

N2 - We investigate Er silicide formed on n-type silicon. In order to protect the Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at temperatures lower than 700 °C. We find that silicidation process is fully completed by rapid thermal annealing at 500 °C. A simplified method of analysis considering the final Schottky barrier MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low apparent Schottky barrier (smaller than 0.1 eV) on a n-type silicon substrate with a concentration of 1.4×10 cm in the active region has been obtained.

AB - We investigate Er silicide formed on n-type silicon. In order to protect the Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at temperatures lower than 700 °C. We find that silicidation process is fully completed by rapid thermal annealing at 500 °C. A simplified method of analysis considering the final Schottky barrier MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low apparent Schottky barrier (smaller than 0.1 eV) on a n-type silicon substrate with a concentration of 1.4×10 cm in the active region has been obtained.

UR - http://www.scopus.com/inward/record.url?scp=0043231388&partnerID=8YFLogxK

U2 - 10.1016/S0038-1101(03)00256-9

DO - 10.1016/S0038-1101(03)00256-9

M3 - Article

AN - SCOPUS:0043231388

VL - 47

SP - 2105

EP - 2111

JO - Solid-State Electronics

JF - Solid-State Electronics

SN - 0038-1101

IS - 11

ER -