Very low Schottky barrier to n-type silicon with PtEr-stack silicide

X. Tang, J. Katcki, Emmanuel Dubois, N. Reckinger, J. Ratajczak, G. Larrieu, P. Loumaye, O. Nisole, V. Bayot

    Research output: Contribution to journalArticlepeer-review

    Abstract

    We investigate Er silicide formed on n-type silicon. In order to protect the Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at temperatures lower than 700 °C. We find that silicidation process is fully completed by rapid thermal annealing at 500 °C. A simplified method of analysis considering the final Schottky barrier MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low apparent Schottky barrier (smaller than 0.1 eV) on a n-type silicon substrate with a concentration of 1.4×10 cm in the active region has been obtained.
    Original languageEnglish
    Pages (from-to)2105-2111
    Number of pages7
    JournalSolid-State Electronics
    Volume47
    Issue number11
    DOIs
    Publication statusPublished - 1 Nov 2003

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