State machine flattening, a mapping study and tools assessment

Research output: Contribution in Book/Catalog/Report/Conference proceedingConference contribution

Abstract

State machine formalisms equipped with hierarchy and parallelism allow to compactly model complex system behaviours. Such models can then be transformed into executable code or inputs for model-based testing and verification techniques. Generated artifacts are mostly flat descriptions of system behaviour. Flattening is thus an essential step of these transformations. To assess the importance of flattening, we have defined and applied a systematic mapping process and 30 publications were finally selected. However, it appeared that flattening is rarely the sole focus of the publications and that care devoted to the description and validation of flattening techniques varies greatly. Preliminary assessment of associated tool support indicated limited tool availability and scalability on challenging models. We see this initial investigation as a first step towards generic flattening techniques and scalable tool support, cornerstones of reliable model-based behavioural development.

Original languageEnglish
Title of host publication2015 IEEE 8th International Conference on Software Testing, Verification and Validation Workshops, ICSTW 2015 - Proceedings
Subtitle of host publicationA-MOST '15
PublisherIEEE
Pages1-8
Number of pages8
ISBN (Print)9781479918850
DOIs
Publication statusPublished - 13 May 2015
Event2015 8th IEEE International Conference on Software Testing, Verification and Validation Workshops, ICSTW 2015 - Graz, Austria
Duration: 13 Apr 201517 Apr 2015

Conference

Conference2015 8th IEEE International Conference on Software Testing, Verification and Validation Workshops, ICSTW 2015
CountryAustria
CityGraz
Period13/04/1517/04/15

Keywords

  • Flattening
  • State machine
  • Systematic Mapping Study

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