Abstract
Charge trapping in self-aligned single-dot memory devices fabricated by UCL technology based on arsenic-assisted etching and oxidation effects is investigated. The devices demonstrate room-temperature single-electron trapping in the Si nanodot floating gate circa 16 nm in size. The pulse transfer (Id-Vg) characteristics and time evolution of the drain current (Id - t) technique are employed for determination of the total charge storage in the Si nanodot floating gate and the gate-nanodot capacitance of the devices.
Original language | English |
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Title of host publication | NATO Security through Science Series B: Physics and Biophysics |
Pages | 251-256 |
Number of pages | 6 |
Publication status | Published - 1 Jan 2006 |