Charge trapping phenomena in single electron NVM SOI devices fabricated by a self-aligned quantum dot technology

A. Nazarov, V. Lysenko, X. Tang, N. Reckinger, V. Bayot

    Research output: Contribution in Book/Catalog/Report/Conference proceedingChapter

    Abstract

    Charge trapping in self-aligned single-dot memory devices fabricated by UCL technology based on arsenic-assisted etching and oxidation effects is investigated. The devices demonstrate room-temperature single-electron trapping in the Si nanodot floating gate circa 16 nm in size. The pulse transfer (Id-Vg) characteristics and time evolution of the drain current (Id - t) technique are employed for determination of the total charge storage in the Si nanodot floating gate and the gate-nanodot capacitance of the devices.
    Original languageEnglish
    Title of host publicationNATO Security through Science Series B: Physics and Biophysics
    Pages251-256
    Number of pages6
    Publication statusPublished - 1 Jan 2006

    Fingerprint

    Dive into the research topics of 'Charge trapping phenomena in single electron NVM SOI devices fabricated by a self-aligned quantum dot technology'. Together they form a unique fingerprint.

    Cite this