A new fabrication method for elevated source/drain junctionless transistors

This paper presents a new, simple and low-cost fabrication method for junctionless transistors. Based on the dopant-assisted etching and oxidation effects, the proposed technique generates a monolithic elevated source/drain (S/D) structure without the addition of any elevation or recession process. More importantly, only one unique implantation creates heavily doped S/D regions and moderately doped channel. The former allows high current flow when the transistor is turned on and the latter ensures full depletion of carriers when the transistor is turned off. The elevation height of S/D regions can be accurately adjusted by the doping energy. The fabricated junctionless transistor with a 130 nm long gate, in which the S/D regions are elevated by 120 nm relatively to the channel, shows impressive performance with an I /I ratio exceeding 10 at V = 1 V and V = 3 V.